The general increase in network traffic requires fast, efficient methods of managing traffic and congestion. One problem area in network traffic management occurs at line switching where a switch is used to route data from one set of communication lines to another set of communication lines. Network switches typically comprise a memory-type device which is used to temporarily store a transmission during the switching operation.
Different queuing structures have been employed in network switches with varying results. It has been shown that switches which use input queue structures tend to create line blocking. Conversely, switches which use output queue architectures eliminate the line blocking problem. Further, switches used in asynchronous transfer mode (ATM) networks require more storage space than switches used in a more uniform transmission network. That is, ATM traffic tends to have bursts of data and be non-uniform, thereby requiring an increased amount of available memory at any given time to maintain an acceptable switching time for the ATM traffic. Poor switch time performance can result in the loss of ATM data during switching operations.
The increased demand for more memory and the need for faster switching times has resulted in the need for a fast, efficient ATM switch Further, the variety of different ATM data cell structures requires that the switch be flexible. One specific problem in ATM switching is the need to change the routing of an ATM cell to avoid highly congested traffic paths. This typically requires that a header included in the ATM cell be amended to denote a new route, or destination address. Additional information included in an ATM cell, such as error check data, may also need to be updated. Further, because memories are susceptible to the inducement of errors, an ATM switch should include an error check scheme to monitor the occurrence of any errors induced during switching.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for an ATM switch which includes flexible redundancy of a complete memory row.